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Agarwal, Harshit
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Preferred name
Agarwal, Harshit
Alternative Name
Agarwal, H.
Main Affiliation
ORCID
Scopus Author ID
53866052200
Researcher ID
K-1743-2017
Now showing 1 - 2 of 2
- PublicationANN-based framework for modeling process induced variation using BSIM-CMG unified model(2024)
;Anant Singhal ;Yogendra Machhiwar ;Shashank Kumar ;Girish PahwaIn this work, we present a machine-learning augmented compact modeling framework for modeling process induced variations in advanced semiconductor devices. The framework employs BSIM-CMG unified compact model at the core and can be used for any advanced devices like GAA nanosheets and nanowires, FinFETs etc. We have validated the model with extensive numerical simulations and experimental data such as 14nm technology FinFET and 24nm technology Nanowire. Our results show excellent accuracy in modeling variability in key electrical parameters of the device including off-current (Ioff), on-current (Ion), threshold voltage (Vth), subthreshold swing (SS) etc. We observe that the overall accuracy of the ML-based framework strongly depends on the nature and physical behavior of the core model used for modeling the nominal device. - PublicationCompact Modeling of Impact Ionization and Conductivity Modulation in LDMOS Transistors(2024)
;Ayushi Sharma ;Yawar Hayat Zarkob ;Girish Pahwa ;Chetan Kumar Dabhi ;Ravi Goel; ;Volker Kubrak ;Mingchun Tang ;Maximilian Treiber ;Chenming HuYogesh Singh ChauhanSpace charge modulation (SCM), that is, the increase of charge carriers in the drift region, modulates carrier concentration in the drift region, which results in conductivity modulation (also known as the expansion effect) of laterally double-diffused metal oxide semiconductor (LDMOS) transistors. In this work: 1) a compact model for conductivity modulation is presented. Since conductivity modulation also causes a change in internal node voltage (d_i ), therefore physics in the impact ionization model of drift region which accurately captures the change in node voltage is also included; 2) an improved model of impact ionization for the intrinsic region of LDMOS transistors (d_i ) is discussed and validated across a high drain voltage for different gate voltages; 3) the topology of the substrate current flow has been modified, in accordance with the device physics; and 4) finally, this work also includes the improved model of the impact ionization to capture the body bias effect in LDMOS transistors. The new model is extensively validated with the experimental and TCAD data. The research aims to enhance the industry-standard Berkeley short-channel IGFET model-bulk (BSIM-BULK) model, ensuring compatibility with SPICE simulators.