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Jitter failure investigation of high speed parallel links in System on Chip environment, modeling and mitigation approach
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Jitter failure investigation of high speed parallel links in System on Chip environment, modeling and mitigation approach
Journal
DesignCon 2015
Date Issued
2015-01-01
Author(s)
Nagpal, Raj Kumar
Damle, Pratik
Tripathi, Jai Narayan
Malik, Rakesh
Mukherjee, Jayanta