NDIE: A Near DRAM Inference Engine Exploiting DIMM's Parallelism

This work aims to design and integrate an inference accelerator in close proximity to the bankgroups of a DIMM. To achieve this integration, we have devised a dataflow that leverages two levels of parallelism. Implementing this approach effectively reduces data access latency and energy consumption. The combined impact of near-DRAM integration and the utilization of two levels of parallelism has resulted in a substantial 21X speedup compared to other DRAM-based approaches.