Optimization of Source/Drain-epi Region Height in GAA Nanosheet FET for RF Applications

As we approach the 3nm technology node, achieving both high ION/IOFF ratio and optimal RF performance in gate-all-around (GAA) nanosheet FET becomes increasingly challenging. As per IEEE International Roadmap for Devices and Systems (IRDS), scaling spacer thickness down to 5nm reduces series resistance. It also leads to an increase in parasitic capacitance (Cpar) negatively impacting RF figures of merit. This work proposes a novel Front-End-Of-Line (FEOL) design approach to mitigate this trade-off. Utilizing 3D TCAD simulations, we demonstrate that adjusting the source/drain-epi height (Hs/d-epi) can significantly improve RF performance without compromising the ION/IOFF ratio. Compared to conventional designs, our optimized GAA nanosheet structure exhibits a 24.88%reduction in Cpar, 3.22% improvement in transconductance (gm), and 13.66% increase in cut-off frequency (Ft), making it a promising candidate for high-performance RF applications at the 3nm node.