On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators

Harmonic cancellation techniques have been exploited for the on-chip generation of high-linearity sinusoidal test stimuli. The sinusoidal signal is generated by combining time-shifted and scaled versions of a periodical signal, in such a way that by properly choosing the time-shifts and weights, the lower order harmonics are canceled. However, process variations and mismatch can degrade the effectiveness of the harmonic cancellation, since precise time-shifts and scale ratios are required. In this regard, timing inaccuracies are especially harmful in the implementation of high-speed harmonic cancelling generators. In this paper, we propose an on-chip calibration architecture that can correct the phase-shift and duty-cycle of the signals with the help of a negative feedback loop. Electrical simulation results at transistor level show the feasibility of the calibration technique for a sinusoidal signal generator implemented in ST 28 nm FD-SOI technology. Obtained results show a Total Harmonic Distortion (THD) better than -60 dB after calibration in an output frequency range from 200 MHz to 4 GHz.