Device Parameters Based Analytical Modeling of Ground-Bounce Induced Jitter in CMOS Inverters

This article presents an analytical approach to estimate jitter in CMOS inverters in the presence of ground-bounce noise (GBN). The relationships between output and input, considering the effect of ground noise, are derived in terms of device parameters for modeling the timing variations. The deviation of each transition edge from the ideal transition edge is modeled using analytical equations to obtain peak-to-peak ground noise induced jitter. To examine the proposed modeling, five case studies are considered for covering the time domain as well as frequency domain estimations. The results obtained using the proposed methodology have a close match with those obtained from the simulations using the electronic design automation (EDA) tool. To claim the independence of proposed modeling with respect to a particular technology, the results are verified at 40, 65, and 180 nm technology nodes of United Microelectronics Corporation (UMC).