Variability-Aware Modeling of Supply Induced Jitter in CMOS Inverters

This study discusses and introduces the impact of variability on power supply-induced jitter in integrated circuits. It presents an analytical approach to model timing uncertainty in the output response of CMOS inverters due to process variations as well as power supply noise. The proposed theory is verified with both simulation and measurement. The proposed approach is not only limited to jitter estimation but it can also be used to analyze the variability issues in CMOS circuits.