A Multiplying Digital to Analog Converter Insensitive to Component Mismatch

A capacitive mismatch insensitive (CMI) multiplying digital to analog converter (MDAC) is proposed in this paper. MDAC requires only four clock phases for 2-bit conversion along with minimal use of circuit components. The reduction in number of clock cycles and improvement in speed is observed at the architecture level as well as circuit level compared to most of the circuits reported in literature. The CMI MDAC is designed and fabricated in AMS 350 nm CMOS process using 3.3 V power supply. The MDAC occupies an area of 70 mu mathrm{m}times 150 mu mathrm{m}. It requires only 240 ns to obtain the residue voltage and consumes 169.5 mu mathrm{W} of power. The proposed MDAC will result in an area efficient and high resolution readout when used in column-parallel cyclic ADC in CMOS image sensors.